1. Field of Invention
Embodiments of the present invention relate to interconnection of multiple application specific integrated circuit (ASIC) devices such as Field Programmable Gate Array (FPGA) devices. More particularly, embodiments of the invention relate to data packet routing methods and systems for routing data between multiple ASIC devices.
2. Description of the Related Art
Reconfigurable ASICs such as FPGA devices are commonly used in signal processing applications, communications applications, interfacing applications, networking applications, and other environments that require and/or benefit from devices that can be user-configured after manufacture. It is common to interconnect multiple FPGA devices as an array on a single circuit card using point-to-point or bussed parallel wiring configurations. Such parallel wiring configurations use many wires, along with associated I/O Counts and termination components, to achieve required data transfer bandwidths, thus requiring the creation of many connection layers on a circuit card leading to undesirable outcomes such as a high degree of mechanical complexity, high cost, and RF interference. Examples of these parallel interfaces include those using signaling standards such as Gunning Transceiver Logic (“GTL”), Stub-Series Termination logic (“SSTL”), and High-Speed Transceiver Logic (“HSTL”). Some of these standards require as many as three termination components per signal to implement.
To alleviate some of the problems of parallel wiring configurations, methods and systems for interconnecting ASIC devices using simplex and/or duplex serial I/O connections, including high speed serial connections such as multi-gigabit serial transceiver (“MGT”) connections have been developed. Such methods and systems achieve communication between given pairs of devices with relatively high data transfer bandwidths and minimal wiring. Furthermore, such methods and systems allow an ASIC card to be easily scalable to other cards to permit easy expansion of ASIC resources.
Circuits having multiple ASIC devices on a single card often require the transfer of large amounts of data between the devices. U.S. Pat. No. 7,444,454 discloses a novel packet router interface switch matric (PRISM) for efficiently routing data packets between multiple FPGA devices or within a single FPGA device. In a PRISM router and similar routers, data is typically sent in data packets of a fixed size. The data accumulates in registers until a sufficient amount of data needed to fill a packet arrives. Then, as soon as a packet can be filled, the packet is assembled and sent using the router.
The data packet creation process requires a certain amount of overhead time. For example, in addition to the time it takes to send a data packet, it may take an additional 25 clock cycles to prepare the packet. The overhead time is relatively constant regardless of the packet size. For example, it takes about the same amount of time to prepare a 100 word packet as a 10 word packet. Thus, it appears that the efficiency of a packet router can be increased by simply increasing the packet size.
Unfortunately, however, larger packet sizes create other problems. For example, while a router waits to receive enough data to fill a large data packet, the destination FPGA device or other device sits idle and wastes processing capabilities. Similarly, waiting for enough data to fill a large data packet may result in lost data. For example, an FPGA device may be configured to add two or more numbers and then send the sum to another FPGA device. The sending FPGA may finish its function and output 50 words of data, but the router may be configured to only route 100 word data packets. The 50 word output of the adder is then held until more is available, and may eventually become lost.